Title :
Pre-characterization procedure for a mixed mode simulation of IR-drop induced delays
Author :
Aparicio, M. ; Comte, M. ; Azais, F. ; Renovell, M. ; Jiang, Jianliang ; Polian, I. ; Becker, B.
Author_Institution :
LIRMM, Univ. of Montpellier, Montpellier, France
Abstract :
This paper presents a procedure of pre-characterization dedicated to the logic and timing simulation of IR-drop induced delays in a logic Block Under Test (BUT) embedded in a chip. The proposed pre-characterization is twofold: the pre-characterization of the library on the one hand and the pre-characterization of the power grid on the other hand. Both should be computed only once for a given technology. Based on this pre-characterization, an original algorithm can be built allowing to perform a per-cycle delay simulation of the logic BUT while taking into account the whole chip IR-drop impact on the simulated block. The simulation is based on a realistic resistive model of the Power Distribution Network (PDN).
Keywords :
distribution networks; logic simulation; logic testing; microprocessor chips; mixed analogue-digital integrated circuits; power grids; timing circuits; IR-drop induced delays; PDN; logic BUT; logic block under test; logic simulation; mixed mode simulation; power distribution network; power grid; pre-characterization procedure; realistic resistive model; simulated block; timing simulation; whole chip IR-drop impact; Capacitance; Computational modeling; Delays; Handheld computers; Logic gates; Power supplies; Switches; Digital CMOS IC; IR-drop; Power Noise; Simulation; Test;
Conference_Titel :
Test Workshop (LATW), 2013 14th Latin American
Conference_Location :
Cordoba
Print_ISBN :
978-1-4799-0595-9
DOI :
10.1109/LATW.2013.6562657
