Analyzing and quantifying fault tolerance properties

Summary form only given. Nanoscale circuit and system design must cope with increasing parameter variations and a growing susceptibility to external noise. To avoid an overly pessimistic design and fully exploit the potential of new technologies, various strategies for “robust” design have been developed in the past few years. Examples range from classical fault tolerant architectures to innovative self-calibrating solutions. However, a robust design style makes validation and test particularly challenging. For design validation, it is no longer sufficient to analyze the functionality, but also robustness properties must be verified. Already the analysis of traditional fault tolerance properties like fault secureness can get very complex. In addition to that, the fault tolerance can vary with the circuit parameters, which makes the analysis extremely difficult. Similarly, manufacturing test has to provide information about the remaining robustness in the presence of manufacturing defects (“quality binning”), and yield estimation should be refined to different quality levels. In this talk we discuss the mentioned problems in more detail for some typical architectures and show first solutions.