Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study

Vertically-stacked Silicon NanoWire FETs (SiNWFETs) with gate-all-around control are the natural and most advanced extension of FinFETs. At advanced technology nodes, due to Schottky contacts at channel interfaces, devices show an ambipolar behavior, i.e., the device exhibits n- and p-type characteristics simultaneously. This property, when controlled by an independent Double-Gate (DG) structure, can be exploited for logic computation, as it provides intrinsic XOR operation. Electrostatic doping of the transistor suppresses the need for dopant implantation at the source and drain regions, which potentially leads to a larger process variations immunity of the devices. In this paper, we propose a novel method based on Technology Computer-Aided Design (TCAD) simulations, enabling the prediction of emerging devices variability. This method is used within our DG-SiNWFET framework and shows that devices, whose polarity is controlled electrostatically, present better immunity to variations for some of their parameters, such as the off-current with 16× less standard deviation.