DocumentCode :
621253
Title :
Evaluating the accuracy of SRAM margin simulation through large scale Monte-Carlo simulations with accurate compact models
Author :
Asenov, P. ; New, David ; Reid, Dave ; Millar, C. ; Roy, Sandip ; Asenov, Asen
Author_Institution :
ARM Ltd., Cambridge, UK
fYear :
2013
fDate :
29-31 May 2013
Firstpage :
29
Lastpage :
32
Abstract :
Accurate statistical compact model extraction and circuit simulation are key issues in contemporary SRAM design. The high statistical variability of the small SRAM cell transistors in combination with high cell density leads to yield problems determined by 5-6σ deviations from the mean. The compact modeling approach presented in this paper utilizes a firm understanding of the physical phenomenon underlying device variability. Its illustration is based on comprehensive `atomistic´ 3D device simulations. Extracted statistical models are then utilized in SRAM dynamic write simulation, and benchmarked against Gaussian VT based simulation, an approach which has been favoured due to its ease of implementation and relative ease of technology characterisation. In addition, the Gaussian VT approach also simplifies statistical analysis and enables margining approaches like Most Probable Vector (MPV), which can drastically reduce simulation time. It is well known that in order to do this, Gaussian VT captures only the 1st order effects of variability, and over estimates the correlation between threshold voltage and other device figures of merit. It is of considerable industrial interest to examine quantitatively the effects of this approximation.
Keywords :
Gaussian processes; Monte Carlo methods; SRAM chips; circuit simulation; network synthesis; Gaussian approach; MPV; SRAM cell transistors; SRAM design; SRAM dynamic write simulation; SRAM margin simulation through large scale Monte Carlo simulations; accurate statistical compact model extraction; atomistic 3D device simulations; cell density; circuit simulation; most probable vector; physical phenomenon; statistical analysis; threshold voltage; Analytical models; Integrated circuit modeling; Logic gates; Random access memory; Semiconductor process modeling; Threshold voltage; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
IC Design & Technology (ICICDT), 2013 International Conference on
Conference_Location :
Pavia
Print_ISBN :
978-1-4673-4740-2
Electronic_ISBN :
978-1-4673-4741-9
Type :
conf
DOI :
10.1109/ICICDT.2013.6563296
Filename :
6563296
Link To Document :
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