• DocumentCode
    621255
  • Title

    Accelerated reliability testing of flash memory: Accuracy and issues on a 45nm NOR technology

  • Author

    Calabrese, M. ; Miccoli, Carmine ; Compagnoni, C. Monzio ; Chiavarone, L. ; Beltrami, S. ; Parisi, A. ; Bartolone, Sebastiano ; Lacaita, Andrea L. ; Spinelli, Alessandro S. ; Visconti, Angelo

  • Author_Institution
    Process RD, Micron Semicond. Italy, Agrate Brianza, Italy
  • fYear
    2013
  • fDate
    29-31 May 2013
  • Firstpage
    37
  • Lastpage
    40
  • Abstract
    This work is focused on the accelerated testing of Flash memory reliability, taking our 45 nm NOR technology as a case study to highlight some major issues that may affect the investigation of modern nanoscale devices. In particular, results will be shown on cycling-induced threshold-voltage instabilities coming from charge trapping/detrapping in the cell tunnel oxide during post-cycling data retention or bake experiments, whose characterization relies on the possibility to reduce the experimental time by an increase of the test temperature according to an Arrhenius law via an activation energy EA. These accelerated characterization schemes come from a detailed physical understanding and modeling of the damage creation/recovery dynamics and rely on the careful evaluation of EA. As shown in the case of the investigated NOR technology, this often does not represent a trivial task, due to the large number of spurious effects affecting the threshold voltage of nanoscale memory cells.
  • Keywords
    NOR circuits; flash memories; integrated circuit reliability; integrated circuit testing; Arrhenius law; NOR technology; accelerated characterization schemes; accelerated reliability testing; activation energy; bake experiments; cell tunnel oxide; charge detrapping; charge trapping; cycling-induced threshold-voltage instabilities; damage creation; flash memory; nanoscale devices; post-cycling data retention; recovery dynamics; size 45 nm; test temperature; Acceleration; Logic gates; Read only memory; Reliability; Testing; Flash memories; program/erase cycling; semiconductor device modeling; semiconductor device reliability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    IC Design & Technology (ICICDT), 2013 International Conference on
  • Conference_Location
    Pavia
  • Print_ISBN
    978-1-4673-4740-2
  • Electronic_ISBN
    978-1-4673-4741-9
  • Type

    conf

  • DOI
    10.1109/ICICDT.2013.6563298
  • Filename
    6563298