Title :
A 10Bit, 10MS/s, low power cyclic ADC
Author :
Chien-Hung Chen ; Wei-Zen Chen
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsin-Chu, Taiwan
Abstract :
A low power, small form factor, cyclic ADC is proposed. By replacing the MDAC with an open loop residual amplifier, it relaxes the gain bandwidth requirement of the operational amplifier to save power. The residual amplifier is background calibrated without extra replica to avoid performance mismatches, and also save area and power. Timing reschedule scheme is proposed for each conversion step to accelerate conversion speed. At 10 MS/s operation, the corresponding FOM is 0.45pJ/conv.-step. Fabricated in a 85nm CMOS technology, the chip size is 0.077mm2.
Keywords :
CMOS integrated circuits; analogue-digital conversion; low-power electronics; operational amplifiers; CMOS technology; low-power cyclic ADC; open loop residual amplifier; operational amplifier; size 85 nm; timing reschedule scheme; word length 10 bit; Benchmark testing; Clocks; Background Calibration; Cyclic ADC; Residual Amplifier;
Conference_Titel :
IC Design & Technology (ICICDT), 2013 International Conference on
Conference_Location :
Pavia
Print_ISBN :
978-1-4673-4740-2
Electronic_ISBN :
978-1-4673-4741-9
DOI :
10.1109/ICICDT.2013.6563326
