Title :
Improvement of gate disturb degradation in SONOS FETs for Vth mismatch compensation in CMOS analog circuits
Author :
Suzuki, M. ; Kinoshita, Akira ; Mitani, Yasunori
Author_Institution :
Corp. R&D Center, Toshiba Corp., Yokohama, Japan
Abstract :
The gate disturb degradation mechanism in silicon-oxide-nitride-oxide-semiconductor (SONOS) FETs with a highprecision threshold voltage (Vth) tuning function, which is designed to compensate for the Vth mismatch in order to achieve high-performance analog circuits, was investigated in detail. A tendency for an unintended positive Vth shift under typical bias conditions in analog circuits was identified. The main cause of the positive Vth shift was determined to be the physical damage induced in the SONOS FETs during programming for Vth tuning. It was found that the use of a thicker block layer effectively suppressed this damage during programming. SONOS FETs that used a thicker block layer to reduce gate disturb degradation demonstrated excellent data retention characteristics, and data retention for ten years could be guaranteed.
Keywords :
CMOS analogue integrated circuits; field effect transistors; CMOS analog circuits; SONOS FET; Vth mismatch; block layer; data retention characteristics; gate disturb degradation mechanism; high-performance analog circuits; highprecision threshold voltage tuning function; mismatch compensation; physical damage; positive Vth shift; silicon-oxide-nitride-oxide-semiconductor FET; typical bias conditions; Analog circuits; Degradation; Field effect transistors; Logic gates; Programming; SONOS devices; Temperature measurement; Analog; SONOS; Vth; data retention;
Conference_Titel :
IC Design & Technology (ICICDT), 2013 International Conference on
Conference_Location :
Pavia
Print_ISBN :
978-1-4673-4740-2
Electronic_ISBN :
978-1-4673-4741-9
DOI :
10.1109/ICICDT.2013.6563335
