A charge sharing based harmonic-reject mixer for RF applications

Harmonic-reject mixers are required in receivers to prevent signals near the LO harmonics from introducing large interferences into the desired signal band. To achieve high attenuation of interferers in harmonic-reject mixers, sub-mixings with accurate gain are required. Existing oversampling harmonic-reject mixer structures employ either three or four mixers with different gains. A harmonic-reject mixer that employs only two mixers with the same gains is proposed to minimize mismatch. Instead of varying the mixer gain, charge sharing is used to implement gain factors with high matching and accuracy. As only two clocks are required for the two signal paths, the layout is greatly simplified and high matching is possible. A prototype circuit has been designed in 65nm CMOS, and the amount of rejection for 3rd and 5th harmonic are simulated to be 44dB and 46dB, respectively. The mixer has a noise figure of 13dB and an IIP3 of -3.1dBm and consumes 11mA at 1.2V supply voltage.