Title :
LP805X: A customizable and low power 8051 soft core for FPGA applications
Author :
Lobo, T. ; Pinto, S. ; Silva, Valter ; Lopes, Salvatore ; Cabral, J. ; Tavares, A. ; Yoowattana, S. ; Sritriratanarak, W. ; Ekpanyapong, M.
Author_Institution :
Centro Algoritmi - University of Minho Portugal
Abstract :
In today´s advanced technological age, embedded and real time systems have become ubiquitous, covering a wide range of applicability. As a result there is an ever growing need for low power capabilities along with reasonable performance, thus presenting a virtual demand for power-aware devices. The purpose of this work was leveraging key techniques and technologies such as design laziness, componentware design, generative design, separation of mechanism and policy, voltage-frequency island, state encoding, clock gating, and operand isolation, and then investigating their effects while designing an energy and power-conscious microcontroller based on 8051 ISA (Instruction Set Architecture) without disregard to silicon area, required application functionalities and performance. Simulations show that our purposed 2 stage pipeline system with built-in hybrid scheduler operates at 230μW@1MHz.
Keywords :
Clocks; Hardware design languages; Memory management; Microcontrollers; Optimization; Power demand; Registers; Processor design; componentware; design laziness; generative design; power and clock gating; power-aware; voltage-frequency island;
Conference_Titel :
Industrial Electronics (ISIE), 2013 IEEE International Symposium on
Conference_Location :
Taipei, Taiwan
Print_ISBN :
978-1-4673-5194-2
DOI :
10.1109/ISIE.2013.6563739