An efficient architecture VLSI for 4×4 intra prediction in HEVC standard

The HEVC is a proposal of new video coding standard that will be used for a wide range of applications like ULTRA HD and 3D applications. MPEG and VCEG have established a Joint Collaborative Team on Video Coding (JCT-VC) to develop the HEVC (High Efficiency Video Coding) standard which is expected to provide a significant improvement in data transmission and streaming efficiency compared to H.264. In this proposal standard, various modules of coding are defined. Among the most complex is the module of the intra prediction. The HEVC defines 35 modes of intra prediction for 8 × 8, 16 × 16, 32 × 32, 3 modes for 64 × 64 and 17 modes for 4 × 4 while the H.264/AVC (Advanced Video Coding) uses 9 modes for intra 4 × 4 and 4 modes for intra 16 × 16. In this paper, we propose an efficient uniform architecture for all of the 4 × 4 intra directional modes. This architecture offers an important gain in case of treatment time compared to the literature. Our proposed architecture is implemented with the technology TSMC 0.18μm CMOS.