Evaluation and implementation of simultaneous binary arithmetic coding and encryption for HD H264/AVC codec

In this paper we propose a new joint video compression and encryption (JVCE) scheme with low-cost FPGA implementation. The encryption technique is based on Randomized Binary Arithmetic Coder (RBAC), which is power and area efficient. This modification of BAC to encrypt each symbol is based on a specific random key, which is generated with LFSR-based PRNG. The encoder scrambles the intervals without making any changes to the width of interval in which the codeword must be included. The compression and encryption processes are executed simultaneously, however in the receiver side we decrypt firstly and then we decode the bitstream. This approach allows us to encrypt information without sacrificing any coding efficiency. This scheme has several advantages compared with other recent schemes. Indeed, the proposed system is fully compliant to H264/AVC codec, with no bit rate reduction. Simulations and FPGA synthesis results show the good robustness of the proposed method.