Overvoltage study of a real HVDC project based MATLAB

For the sake of ensuring the operation reliability and stability of high voltage direct current (HVDC) power transmission system, it is needed and meaningful to study the overvoltage characteristics of HVDC system under abnormal condition. In this paper, the different reasons causing the HVDC overvoltage are introduced in brief, and aiming at the ±500kV HVDC project from Jiangling to Echeng, its overvoltage characteristics under different fault conditions are simulated based on MATLAB/SIMULINK. Besides, the influence of changing the HVDC control system´s running parameter on the overvoltage´s peak amplitude is investigated preliminarily. According to the simulation results, the overvoltage level of the selected ±500kV HVDC project is within the acceptable range, and along with the decrease of the current-limitation parameter in voltage dependent current order limiter (VDCOL), the HVDC overvoltage will increase slowly.