Design of dual redundancy CAN-bus controller based on FPGA

Author

Han Xiang-Dong ; Yuan Hui-mei ; Zhao Xiao-Xu

Author_Institution

Coll. of Inf. Eng., Capital Normal Univ., Beijing, China

fYear

2013

fDate

19-21 June 2013

Firstpage

843

Lastpage

847

Abstract

At present, the technique of dual redundancy CAN-bus is mainly implemented by software, so that it has the disadvantages of low reliability and bad real-time performance. Built on the error handling rule in CAN specification version 2.0, a hardware redundancy management unit is creatively put forward in this paper. Based on FPGA, a kind of customized Dual Redundancy CAN-bus Controller (DRCC) is designed. By downloading the IP Core into a XILINX´s SPARTAN-3 chip to test, it has been verified that the design could completely meet the requirement for high real-time performance and reliability, with a bright prospect for the future.

Keywords

controller area networks; error handling; field buses; field programmable gate arrays; integrated circuit reliability; redundancy; CAN specification version 2.0; DRCC design; FPGA; IP Core; XILINX SPARTAN-3 chip; dual-redundancy CAN-bus controller design; error handling rule; hardware redundancy management unit; Field programmable gate arrays; Hardware design languages; IP networks; Radiation detectors; Real-time systems; Redundancy; Switches; Dual Redundancy CAN-bus; FPGA; IP Core; Verilog;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Electronics and Applications (ICIEA), 2013 8th IEEE Conference on

Conference_Location

Melbourne, VIC

Print_ISBN

978-1-4673-6320-4

Type

conf

DOI

10.1109/ICIEA.2013.6566484

Filename

6566484