Architectural synthesis of networks on chip

The current systems are very complex and feature a high degree of communications. Because the bus is a critical and shared resource, it can no longer cope with the requirements of applications for which the bandwidth is a critical parameter. An intermediate solution was to use cross-bars but was also rejected in favor of more interesting solutions: using a network on chip (NOC) in order to meet the specific requirements of the involved application in terms of surface, power consumption and bandwidth. To do this, several methodologies have been defined and are mainly based on mesh networks, fat trees and their variants. In this context, we have proposed an alternative methodology [14] which distinguishes itself from others by several points, especially by the data routing. In this paper, we present our synthesis method of the network architecture whose components (floorplanning of the IPs, number and size of the interconnections) were previously generated during design space exploration. This synthesis was conducted targeting TSMC 0.18 μm technology process.