On-chip 20Gbps high-speed I/O IC test system for signal integrity characterization in flip-chip package

This paper focuses on signal integrity characterization using On-chip 20Gbps high-speed I/O embedded test structures in a flip-chip package. The authors designed On-chip 20Gbps High-Speed I/O Test IC that consists of 20GHz PLL (Phase Locked Loop), 20Gbps PRBS (Pseudo Random Bit Sequence) Generator and 4-port 20Gbps differential CML (Current Mode Logic) I/O. The test IC is designed and simulated in UMC 90nm technology. In addition, the author modeled a test vehicle on to Android Rogers 4350B PCB which is 50Ω matched in HFSS. The vehicle has two patterns; one is a differential microstrip lines pattern which has two different lengths of differential pair traces, the other is differential microstrip lines with multiple vias. Using the test IC and the vehicle, the paper is presented both transient and electromagnetic simulation results for characterizing the signal integrity in flip-chip package.