Abstract :
Summary form only given. As we move to higher levels of integration, it is clear that power and energy efficiency are the most formidable barriers. A chip built out of 1000 cores requires fundamentally rethinking the whole compute stack from the ground up for energy efficiency. Often, energy efficiency is in direct conflict with resilience. In this talk, I will describe some of the architecture technologies that we are exploring, based on low voltage operation and streamlined architectures.
Conference_Titel :
Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International Conference on