Title :
Enabling development of OpenCL applications on FPGA platforms
Author :
Shagrithaya, Kavya ; Kepa, Krzysztof ; Athanas, Peter
Author_Institution :
Bradley Dept. of ECE, Virginia Tech, Blacksburg, VA, USA
Abstract :
High-level FPGA synthesis tools aim to increase the productivity of FPGAs and to adopt them among software developers and domain experts. OpenCL is a specification introduced for parallel programming across heterogeneous platforms. In this paper, an automated compilation flow to generate customized application-specific hardware descriptions from OpenCL computation kernels is reported. The flow uses Xilinx AutoESL tool to obtain the design specification for OpenCL kernel cores. The provided architecture integrates generated cores with memory and OpenCL host application interfaces. The host program in the OpenCL application is compiled and executed to demonstrate a proof-of-concept implementation towards achieving an end-to-end flow that provides abstraction of hardware at the front-end.
Keywords :
computer interfaces; field programmable gate arrays; integrated circuit design; parallel programming; OpenCL kernel cores; Xilinx AutoESL tool; automated compilation flow; customized application-specific hardware descriptions; design specification; domain experts; field programmable gate arrays; heterogeneous platforms; high-level FPGA synthesis tools; host application interfaces; host program; memory; parallel programming; proof-of-concept implementation; software developers; Computer architecture; Field programmable gate arrays; Graphics processing units; Hardware; Kernel; Parallel processing; Vectors; AutoESL; Convey; FPGA; HPC; OpenCL; Vivado; source-to-source translation;
Conference_Titel :
Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International Conference on
Conference_Location :
Washington, DC
Print_ISBN :
978-1-4799-0494-5
DOI :
10.1109/ASAP.2013.6567546
