Pseudo-constant logic optimization

Constant folding reduces area and enables greater parallelism, but requires circuits with constant inputs. In this work, we extend constant folding to support pseudo-constants, which are values that change with low frequency. We present a method of pseudo-constant logic optimization based on dynamically reconfigurable capabilities of FPGAs, which optimizes logic for different pseudo-constant values and then reconfigures the logic whenever the pseudo-constant changes. Although not beneficial for all logic, we show this optimization achieves up to a 1.25x increase in functional density on Xilinx Virtex 5 FPGAs.