DocumentCode
624349
Title
FARHAD: A Fault-Tolerant Power-Aware Hybrid Adder for add intensive applications
Author
Hajkazemi, Mohammad H. ; Baniasadi, Amirali ; Asadi, Hamed
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Victoria, Victoria, BC, Canada
fYear
2013
fDate
5-7 June 2013
Firstpage
153
Lastpage
159
Abstract
This paper introduces an alternative FaultTolerant Power-Aware Hybrid Adder (or simply FARHAD). FARHAD is a highly power efficient protection solution against errors in application with high number of additions. FARHAD, similar to earlier studies, relies on performing add operations twice to detect errors. Unlike previous studies, FARHAD uses an aggressive adder to produce the initial outcome and a low-power adder to generate the second outcome, referred to as the checker. FARHAD uses checkpointing, a feature already available to high-performance processors, to recover from errors. FARHAD achieves the high energy-efficiency of time-redundant solutions and the high performance of resource-redundant adders. We evaluate FARHAD from power and performance points of view using a subset of SPEC´2K benchmark. Our evaluations show that FARHAD outperforms an alternative time-redundant solution by 20%. FARHAD reduces the power dissipation of an alternative resource-redundant adder by 40% while maintaining performance.
Keywords
adders; checkpointing; electronic engineering computing; energy conservation; fault tolerant computing; low-power electronics; parallel processing; power aware computing; FARHAD; SPEC´2K benchmark; add intensive applications; alternative resource-redundant adder; checkpointing; energy-efficiency; error detection; fault-tolerant power-aware hybrid adder; high-performance processors; low-power adder; power dissipation; power efficient protection solution; resource-redundant adders; time-redundant solutions; Adders; Benchmark testing; Fault tolerance; Power dissipation; Program processors; Tunneling magnetoresistance; fault-tolerant adders; low-power design; power-aware reliability;
fLanguage
English
Publisher
ieee
Conference_Titel
Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International Conference on
Conference_Location
Washington, DC
ISSN
2160-0511
Print_ISBN
978-1-4799-0494-5
Type
conf
DOI
10.1109/ASAP.2013.6567569
Filename
6567569
Link To Document