Power optimization of sum-of-products design for signal processing applications

Author

Seok Won Heo ; Suk Joong Huh ; Ercegovac, Milos D.

Author_Institution

Comput. Sci. Dept., Univ. of California at Los Angeles, Los Angeles, CA, USA

fYear

2013

fDate

5-7 June 2013

Firstpage

192

Lastpage

197

Abstract

Power consumption is a critical aspect in today´s mobile environment, while high-throughput remains a major design goal. To satisfy both low-power and high-throughput requirements, parallelism has been employed. In this paper we present an approach to reducing power dissipation in the design of sum-of-products operation by utilizing parallel hardware while maintaining high-throughput. The proposed design reduces about 46% of execution time with about 12% energy penalty compared to the ARM7TDMI-S multipliers in benchmark programs.

Keywords

parallel processing; power aware computing; signal processing; ARM7TDMI-S multipliers; energy penalty; mobile environment; parallel hardware; power consumption; power dissipation; power optimization; signal processing application; sum of products design; Adders; Benchmark testing; Clocks; Delays; Finite impulse response filters; Hardware; Power dissipation; High-throughput Arithmetic; Low-power Arithmetic; Sum-of-products;

fLanguage

English

Publisher

ieee

Conference_Titel

Application-Specific Systems, Architectures and Processors (ASAP), 2013 IEEE 24th International Conference on

Conference_Location

Washington, DC

ISSN

2160-0511

Print_ISBN

978-1-4799-0494-5

Type

conf

DOI

10.1109/ASAP.2013.6567574

Filename

6567574