Hybrid SPM-cache architectures to achieve high time predictability and performance

Time predictability and performance are usually two conflicting goals. In this paper, we propose an on-chip hybrid SRAM architecture by putting a small cache and a small ScratchPad Memory (SPM) together. Our evaluation indicates that with the equivalent total on-chip storage size, the time predictability of most hybrid architectures is better than that of caches only, and the performance of most hybrid architectures is better than that of SPMs only. Moreover, we find that for some benchmarks, the SPM and the cache can cooperate effectively in the hybrid architectures to achieve performance superior to the cache-only architecture.