A hardware test platform in field-programmable logic for parallelized digital signal processing

This paper describes the development and application of a self-contained platform to support hardware implementation and testing of components and systems for parallelized digital signal processing in field-programmable gate-array (FPGA) logic chips. To more closely reflect the usage of parallelized components in actual applications, high-speed input/output pins of FPGA chips are utilized in a loopback configuration so that parallel streams of representative digitized complex fixed-point data are fed as input to a system under test. Onchip FPGA memory is used to implement high-speed FIFO buffers connected to the system under test. On-chip memory is also used to stage data for the input FIFO buffer feeding the system under test and to collect processed data from the output FIFO buffer. An embedded processor executes software used to perform data transfers between the FIFO buffers and staging memory, and to initiate full-speed operation for a system under test with data flowing through the external loopback connection. This paper also provides sample results from a representative parallelized finite-impulse-response filter tested using the hardware platform described in this paper.