A variable block-size design of HEVC transform using intra-coefficient sharing

In this brief, we present a reconfigurable architecture to implement variable block-size transforms (8-point, 16-point and 32-point) in HEVC. The scheme is based on internal sharing and reuse of transform coefficients and uses a novel two-level grouping strategy exploiting the mirror symmetry and mirror anti-symmetry of the coefficients. Additionally, we have adopted an adder-share strategy in the core processing module to save implementation cost. The proposed scheme is implemented using 0.18um CMOS technology and produces comparatively better results with all existing designs.