A layout-aware x-filling approach for dynamic power supply noise reduction in at-speed scan testing

Power Supply Noise (PSN) has emerged as an important resilience issue in nano-scale CMOS technology. Due to simultaneous switching of various gates, the actual supply voltage seen by individual gates inside the circuit might be lower than the nominal supply voltage, leading to extra delays. Since in at-speed scan testing simultaneous switchings are higher than the functional mode, test invalidation due to excessive PSN can happen, which may impact yield loss. In this paper, we propose a Linear Programming-based X-filling approach to minimize PSN in at-speed scan test by assigning appropriate values to X-bits in partially specified test patterns. In this paper, spatial and transition time correlations due to circuit layout, power mesh, and netlist are taken into account to increase the accuracy of dynamic PSN estimation and for the first time the delay of the circuit is directly targeted to minimize the effect of PSN during the at-speed scan test.