DocumentCode :
625264
Title :
Reconciling the IC test and security dichotomy
Author :
Sinanoglu, Ozgur ; Karimi, N. ; Rajendran, Jeyavijayan ; Karri, Ramesh ; Jin, Yichao ; Huang, Kejie ; Makris, Yiorgos
Author_Institution :
NYU, Abu Dhabi, United Arab Emirates
fYear :
2013
fDate :
27-30 May 2013
Firstpage :
1
Lastpage :
6
Abstract :
Many of the design companies cannot afford owning and acquiring expensive foundries and hence, go fabless and outsource their design fabrication to foundries that are potentially untrustwrothy. This globalization of Integrated Circuit (IC) design flow has introduced security vulnerabilities. If a design is fabricated in a foundry that is outside the direct control of the (fabless) design house, reverse engineering, malicious circuit modification, and Intellectual Property (IP) piracy are possible. In this tutorial, we elaborate on these and similar hardware security threats by making connections to VLSI testing. We cover design-for-trust techniques, such as logic encryption, aging acceleration attacks, and statistical methods that help identify Trojan´ed and counterfeit ICs.
Keywords :
VLSI; ageing; industrial property; integrated circuit design; integrated circuit testing; logic circuits; logic design; reverse engineering; security; statistical analysis; IC design; IC testing; IP; Trojan´ed identification; VLSI testing; aging acceleration attack; design-for-trust technique; hardware security threat; integrated circuit design flow; integrated circuit fabrication; intellectual property piracy; logic encryption; malicious circuit modification; reverse engineering; security dichotomy vulnerability; statistical method; Aging; Encryption; Foundries; Hardware; Integrated circuits; Logic gates; Semiconductor device measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ETS), 2013 18th IEEE European
Conference_Location :
Avignon
Print_ISBN :
978-1-4673-6376-1
Type :
conf
DOI :
10.1109/ETS.2013.6569368
Filename :
6569368
Link To Document :
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