Title :
New test compression scheme based on low power BIST
Author :
Tyszer, J. ; Filipek, Michal ; Mrugalski, Grzegorz ; Mukherjee, Nandini ; Rajski, J.
Author_Institution :
Poznan Univ. of Technol., Poznań, Poland
Abstract :
This paper describes a new programmable low power test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the existing logic BIST infrastructure. The proposed hybrid scheme efficiently combines test compression with logic BIST, where both techniques can work synergistically to deliver high quality test. Experimental results obtained for industrial designs illustrate feasibility of the proposed test scheme and are reported herein.
Keywords :
built-in self test; logic circuits; logic design; logic testing; low-power electronics; programmable circuits; industrial design; low power logic BIST infrastructure; programmable low power test compression method; quality testing; test power envelope shaping; Built-in self-test; Encoding; Latches; Phase shifters; Registers; Ring generators; Switches; Built-in self-test; hybrid low power compression; low power test; scan-based test; test data compression; toggling;
Conference_Titel :
Test Symposium (ETS), 2013 18th IEEE European
Conference_Location :
Avignon
Print_ISBN :
978-1-4673-6376-1
DOI :
10.1109/ETS.2013.6569374
