Author :
Joshi, K. ; Hung, S. ; Mukhopadhyay, S. ; Sato, T. ; Bevan, M. ; Rajamohanan, B. ; Wei, A. ; Noori, A. ; McDougall, B. ; Ni, C. ; Lazik, C. ; Saheli, G. ; Liu, P. ; Chu, D. ; Date, L. ; Datta, S. ; Brand, A. ; Swenberg, J. ; Mahapatra, S.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol. Bombay, Mumbai, India
Abstract :
The impact of gate insulator processes to achieve deeply scaled interlayer (IL)/high-k (HK) bilayer stacks for sub-20-nm CMOS on negative-bias temperature instability and positive-bias temperature instability is studied. IL scaling is done by novel low-thermal-budget rapid-thermal-process-based ultrathin IL and monolayer IL. Innovative IL top surface treatment enables integration of IL and atomic-layer-deposition-based hafnium oxide HK without vacuum break. Fully integrated stacks show scaling of equivalent oxide thickness down to ~6Å, with excellent gate leakage, mobility, and world-class BTI. The mechanism responsible for improved BTI is discussed.
Keywords :
CMOS logic circuits; atomic layer deposition; hafnium compounds; CMOS logic applications; HfOx; IL-HK bilayer stacks; atomic-layer-deposition-based hafnium oxide; gate insulator processes; innovative IL top surface treatment; low-thermal-budget rapid-thermal-process; monolayer IL; negative-bias temperature instability; positive-bias temperature instability; scaled gate stacks; scaled interlayer-high-k bilayer stacks; size 20 nm; thermal IL integration; ultrathin IL; Electron traps; Gate leakage; Hafnium compounds; Logic gates; MOSFET circuits; Stress; DCIV; HKMG; equivalent oxide thickness (EOT) scaling; flicker noise; gate leakage; interlayer (IL) scaling; mobility; negative-bias temperature instability (NBTI); positive-bias temperature instability (PBTI);
