• DocumentCode
    625439
  • Title

    A 20Gb/s 136fJ/b 12.5Gb/s/μm on-chip link in 28nm CMOS

  • Author

    Nazari, Masoud Honarvar ; Emami-Neyestanak, A.

  • Author_Institution
    Electr. Eng. Dept., California Inst. of Technol., Pasadena, CA, USA
  • fYear
    2013
  • fDate
    2-4 June 2013
  • Firstpage
    257
  • Lastpage
    260
  • Abstract
    A high data rate, low power on-chip link in 28nm CMOS is presented. It features a double-sampling receiver with dynamic offset modulation and a capacitively-driven transmitter. The functionality of the link was validated using 4-7mm minimum-pitch on-chip wires. It achieves up to 20Gb/s of data rate (13.9Gb/s/μm) with BER<; 10-12. It has better than 136fJ/b of power efficiency at 10Gb/s. The total area of the transmitter and receiver is 1110μm2.
  • Keywords
    CMOS integrated circuits; error statistics; modulation; BER; CMOS; bit rate 12.5 Gbit/s; bit rate 20 Gbit/s; capacitively-driven transmitter; double-sampling receiver; dynamic offset modulation; on-chip link; size 28 nm; Bandwidth; Capacitors; Modulation; Power demand; Receivers; System-on-chip; Wires; Crosstalk; Double-sampling; Dynamic offset modulation; Interconnect; On-chip signaling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Radio Frequency Integrated Circuits Symposium (RFIC), 2013 IEEE
  • Conference_Location
    Seattle, WA
  • ISSN
    1529-2517
  • Print_ISBN
    978-1-4673-6059-3
  • Type

    conf

  • DOI
    10.1109/RFIC.2013.6569576
  • Filename
    6569576
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=625439