A sub-1mw 5.5-GHz PLL with digitally-calibrated ILFD and linearized varactor for low supply voltage operation

This paper proposes an ultra-low-power 5.5GHz PLL which employs a divide-by-4 injection-locked frequency divider (ILFD) and linearity-compensated varactor for low supply voltage operation. The digital calibration circuit is introduced to control the ILFD frequency automatically. The proposed varactor, which applies a forward-body-bias (FBB) technique, is employed for linear-frequency-tuning under the power supply of 0.5 V. The proposed PLL was fabricated in 65 nm CMOS. With a 34.3-MHz reference, it shows a 1-MHz-offset phase noise of -106 dBc/Hz, a reference spur level lower than -65 dBc, and the total power consumption of 950μW at 5.5 GHz.