• DocumentCode
    625636
  • Title

    A Theoretical Framework for Algorithm-Architecture Co-design

  • Author

    Czechowski, Kenneth ; Vuduc, Richard

  • Author_Institution
    Sch. of Comput. Sci. & Eng., Georgia Inst. of Technol., Atlanta, GA, USA
  • fYear
    2013
  • fDate
    20-24 May 2013
  • Firstpage
    791
  • Lastpage
    802
  • Abstract
    We consider the problem of how to enable computer architects and algorithm designers to reason directly and analytically about the relationship between high-level architectural features and algorithm characteristics. We propose a modeling framework designed to help understand the long-term and high-level impacts of algorithmic and technology trends. This model connects abstract communication complexity analysis-with respect to both the inter-core and inter-processor networks and the memory hierarchy-with current technology proposals and projections. We illustrate how one might use the framework by instantiating a particular model for a class of architectures and sample algorithms (three-dimensional fast Fourier transforms, matrix multiply, and three-dimensional stencil). Then, as a suggestive demonstration, we analyze a number of what-if scenarios within the model in light of these trends to suggest broader statements and alternative futures for power-constrained architectures and algorithms.
  • Keywords
    computer architecture; fast Fourier transforms; matrix multiplication; abstract communication complexity analysis; algorithm-architecture codesign; algorithmic trend; high-level architectural feature; intercore processor network; interprocessor network; matrix multiply; memory hierarchy; modeling framework; power-constrained architecture; technology trend; three-dimensional fast Fourier transforms; three-dimensional stencil; Algorithm design and analysis; Analytical models; Bandwidth; Computational modeling; Computer architecture; Mathematical model; System-on-chip; algorithm-architecture codesign; exascale;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel & Distributed Processing (IPDPS), 2013 IEEE 27th International Symposium on
  • Conference_Location
    Boston, MA
  • ISSN
    1530-2075
  • Print_ISBN
    978-1-4673-6066-1
  • Type

    conf

  • DOI
    10.1109/IPDPS.2013.99
  • Filename
    6569862