A 0.5-V 5.5-GHz class-C-VCO-based PLL with ultra-low-power ILFO in 65 nm CMOS

In this paper, an ultra-low-power 5.5-GHz PLL is proposed which employs the new divide-by-4 injection-locked frequency divider (ILFD) and a class-C VCO for operation under a power supply of 0.5 V. A forward-body-biasing (FBB) technique can decrease threshold voltage of MOS transistors, which can improve operation frequency and can widen the lock range of the ILFD. The double-switch injection technique is also proposed to widen the lock range of the ILFD. The proposed PLL was fabricated in 65nm CMOS. The whole circuit consumes 1.6 mW under the power supply of 0.5V. With a 34.6-MHz reference, it shows a 1-MHz-offset phase noise of -105 dBc/Hz and a reference spur level lower than -65dBc at 5.5 GHz.