Title :
A merged first and second stage for low power pipelined ADC
Author :
Changyi Yang ; Weitao Li ; Fule Li ; Zhihua Wang
Author_Institution :
Tsinghua Nat. Lab. for Inf. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
This paper proposes a merged first and second stage for pipelined ADC. It merges the first MDAC and second MDAC by using opamp and capacitor sharing technique to reduce power. For low supply advanced CMOS technology, the range-scaling technique is used to reduce output range in this stage, so the single-stage opamp can be used with low supply voltage to reduce power furthermore. The SHA-less technique is also used for the reduction of power and noise. The proposed stage relaxes the requirement for the gain of opamp by about 6dB comparing to the conventional one. For verification, a 14bit, 200MS/s pipelined ADC is designed in a 130nm CMOS process. The simulation results show 73.4 dB SNDR with noise and 88.8dBc SFDR at 95 MHz input frequency. The pipelined core power consumption is about 42mW at 1.2V supply, and the whole pipelined ADC has an energy efficiency of 178 fJ/conversion-step.
Keywords :
CMOS analogue integrated circuits; analogue-digital conversion; low-power electronics; operational amplifiers; MDAC; SFDR; SHA-less technique; SNDR; bit rate 200 Mbit/s; capacitor sharing technique; frequency 95 MHz; low power pipelined ADC; low supply advanced CMOS technology; power reduction; range-scaling technique; single-stage opamp sharing technique; size 130 nm; voltage 1.2 V; word length 14 bit; CMOS integrated circuits; CMOS technology; Capacitors; Discharges (electric); Equations; Gain; Noise;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6571805