FDSOI versus BULK CMOS at 28 nm node which technology for ultra-low power design?

Author

Makipaa, Jani ; Billoint, O.

Author_Institution

VTT (Nat. Res. Centre of Finland), Espoo, Finland

fYear

2013

fDate

19-23 May 2013

Firstpage

554

Lastpage

557

Abstract

Compared to BULK CMOS, FDSOI (Fully-Depleted Silicon-On-Insulator) introduces an ultra-thin buried oxide (BOX) layer and a dopant-free channel, which provides better performance and enhances ultra-low power (ULP) operation. To investigate benefits of utilizing FDSOI for ULP design, FDSOI and BULK CMOS 28 nm nodes are compared by simulating a test circuit. Threshold voltage tuning by back-plane biasing (BPB) for FDSOI and bulk biasing (BB) for BULK is analyzed. Contours of constant energy with minimum energy points (MEPs) are shown as well as energy delay products (EDPs). Simulation results show that FDSOI forward BPB can be used effectively to control operating frequency, EDP and MEP operation. Implications of the results are discussed last to give an overview how FDSOI performance gain over BULK CMOS can support in ULP design.

Keywords

CMOS integrated circuits; integrated circuit design; low-power electronics; silicon-on-insulator; BULK CMOS technology; EDP operation; FDSOI; MEP operation; ULP design; back plane biasing; constant energy; dopant free channel; energy delay product; fully depleted silicon-on-insulator; minimum energy point; operating frequency control; size 28 nm; ultralow power design; ultralow power operation; ultrathin buried oxide layer; CMOS integrated circuits; CMOS technology; Conferences; Delays; Low-power electronics; Threshold voltage; Tuning; BULK; FDSOI; Minimum energy operation; back plane biasing; bulk biasing; sub-threshold operation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2013 IEEE International Symposium on

Conference_Location

Beijing

ISSN

0271-4302

Print_ISBN

978-1-4673-5760-9

Type

conf

DOI

10.1109/ISCAS.2013.6571903

Filename

6571903