DocumentCode :
626583
Title :
Minimum energy point tracking for sub-threshold digital CMOS circuits using an in-situ energy sensor
Author :
Mehta, Neerav ; Makinwa, Kofi A. A.
Author_Institution :
Electron. Instrum. Lab., Delft Univ. of Technol., Delft, Netherlands
fYear :
2013
fDate :
19-23 May 2013
Firstpage :
570
Lastpage :
573
Abstract :
The design of an energy sensor and a minimum energy point tracking algorithm are presented. When synthesized with standard cells in a 0.13μm CMOS process, the tracking algorithm requires 2021 gates (0.008mm2), which consume 32μW when clocked at 100MHz. The proposed energy sensor operates by integrating the voltage drop across a power gating device. A digitally-assisted integrator ensures a wide dynamic range. When operated from a 1.2V supply, the sensor dissipates only 80μW, which is further reduced by a comparator-sharing scheme. The sensor has a resolution of 10fJ and can resolve 0.0025 activity changes in a 0.7MHz bandwidth.
Keywords :
CMOS integrated circuits; comparators (circuits); digital integrated circuits; electric potential; bandwidth 0.7 MHz; comparator-sharing scheme; digitally-assisted integrator; frequency 100 MHz; in-situ energy sensor; minimum energy point tracking; power 32 muW; power 80 muW; power gating device; size 0.13 mum; standard cells; subthreshold digital CMOS circuits; tracking algorithm; voltage 1.2 V; voltage drop; Algorithm design and analysis; Clocks; Dynamic range; Energy consumption; Heuristic algorithms; Integrated circuit modeling; Logic gates;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
ISSN :
0271-4302
Print_ISBN :
978-1-4673-5760-9
Type :
conf
DOI :
10.1109/ISCAS.2013.6571906
Filename :
6571906
Link To Document :
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