A fully differential CMOS self-biased two-stage preamplifier-latch threshold detection comparator

A novel CMOS threshold detection comparator topology composed of a two-stage preamplifier cascaded with a latch is presented in this paper. It exploits the best aspects of its sub-blocks to achieve low delays. The proposed circuit is fully differential and possesses desired properties like high input resistance and rail-to-rail output swing, low offset and (kickback) noise, etc. Moreover, the comparator is also truly self-biased through a negative feedback loop which makes it resistant to PVT variations. Since the comparator features high speed under relatively low power consumption and occupies small die area, it is suitable for use in modern SoC data converters/transceivers.