Low power, high linearity multi-mode downconversion mixer for SDR

Author

Yexin Chen ; Na Yan ; Jianfei Xu ; Qiang Chen ; Jie Sun

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2013

fDate

19-23 May 2013

Firstpage

737

Lastpage

740

Abstract

A low-power, high linearity and wideband passive mixer for SDR is presented The passive mixer employs the improved current-reuse Gm stage, combines source degeneration with MGTR to extend the linearity region while enhance the IIP₃ performance Measured results show the design achieves a good linearity even though the power of input RF signal is up to -14dBm (V_pp is about 160mV, consider the balun´s voltage gain and insert loss). The passive mixer achieves 10.7-13.8 dBm IIP₃, IIP2 > 44dB, and 13.7dB NF under 13dB Max conversion gain at 900MHz. Implemented in 65nm CMOS process, the mixer core die area is 0.2mm², and consumes 6.7mA from a 1.2V supply.

Keywords

CMOS integrated circuits; UHF mixers; software radio; CMOS process; IIP₃ performance; MGTR; SDR; current 6.7 mA; frequency 900 MHz; gain 13 dB; high linearity multi-mode downconversion mixer; improved current-reuse Gm stage; input RF signal power; low power mixer; noise figure 13.7 dB; passive mixer; size 65 nm; voltage 1.2 V; Linearity; Mixers; Noise; Radio frequency; Receivers; Resistors; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2013 IEEE International Symposium on

Conference_Location

Beijing

ISSN

0271-4302

Print_ISBN

978-1-4673-5760-9

Type

conf

DOI

10.1109/ISCAS.2013.6571952

Filename

6571952