Implementation of hybrid version management in hardware transactional memory

Transactional Memory (TM) has been proposed as an alternative to locks to simplify parallel programming. While most research has focused on the architectural support of TM, it is at least equally important to investigate the hardware implementation of the key mechanisms of TM to facilitate its deployment in commercial processors. In this paper, we present a light-weight and generic implementation of the key structures to support hybrid version management in Hardware Transactional Memory (HTM). Full-system simulation demonstrates the performance advantage of our design (up to 40% improvement). Synthesis results show that the hardware structures incur an area overhead of only 0.4% and a power overhead of 1.65% to the Sun Rock processor design.