Design of a third-order ΣΔ modulator with minimum op-amps output swing

Author

Belotti, Oscar ; Bonizzoni, Edoardo ; Maloberti, Franco

Author_Institution

Dipt. di Ing. Ind. e dell´Inf., Univ. of Pavia, Pavia, Italy

fYear

2013

fDate

19-23 May 2013

Firstpage

821

Lastpage

824

Abstract

This paper presents the design of a third-order ΣΔ modulator targeted for WCDMA applications. The architecture uses two operational amplifiers and distributed fully digital feed-forward paths to minimize the output swing of op-amps. Simulation results show that first and second integrator output swings are reduced by 88% and 75%, respectively. Post-layout simulation results of the modulator, designed in 65-nm CMOS technology, give a SNDR of 83 dB over a signal bandwidth of 2.2 MHz. The power consumption is 2.3 mW and the achieved FoM is equal to 172.8 dB.

Keywords

CMOS analogue integrated circuits; code division multiple access; operational amplifiers; sigma-delta modulation; CMOS technology; FoM; SNDR; WCDMA applications; distributed fully digital feedforward paths; first integrator output swings; minimum opamp output swing; operational amplifiers; post-layout simulation; power 2.3 mW; second integrator output swings; size 65 nm; third-order ΣΔ modulator design; Bandwidth; Modulation; Noise; Power demand; Quantization (signal); Switches; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2013 IEEE International Symposium on

Conference_Location

Beijing

ISSN

0271-4302

Print_ISBN

978-1-4673-5760-9

Type

conf

DOI

10.1109/ISCAS.2013.6571973

Filename

6571973