Two-stage charge sensitive amplifier with self-biased MOS transistor as continuous reset system

A two-stage charge sensitive amplifier architecture suitable for semiconductor radiation detector with large capacitance is proposed. The integration capacitor of the first stage can be made large to reduce gain sensibility to detector capacitance without any stability problem. Each stage uses a self-biased MOS transistor to discharge the integration capacitor. The self-bias circuit tracks process, temperature and supply voltage variations to make a relatively constant feedback resistor. This improves the gain linearity of the charge sensitive amplifier and the uniformity of multi-channel front-end electronics. The feasibility of the proposed circuit is verified by comparing the simulation results with the conventional one-stage charge sensitive amplifier and a two-stage structure with fixed-gate-voltage reset transistor. A prototype of 16-channel front-end circuit for electron collection designed in a 0.35μm CMOS technology has been measured. The area is 2.5×1.54mm² with 42 pads and the power dissipation is 60mW with power supplies of 2V and 5V.