Title :
Hardware implementation for real-time 3D rendering in 2D-to-3D conversion
Author :
Yeong-Kang Lai ; Yu-Chieh Chung ; Yu-Fan Lai
Author_Institution :
Dept. of Electr. Eng., Nat. Chung Hsing Univ., Taichung, Taiwan
Abstract :
With the advances in central processing unit (CPU) capability, 3D display technology becomes popular in recent years. Now, there are more and more 3D products such as 3D camera, 3D projector, and 3D-TV. The 3D technology is not difficult to understand because most of the video contents are captured through two individual lenses. The corresponding video contents are considered as two respective bit streams. However, how to transform traditional 2D video contents to 3D one is a critical problem to solve it. This paper proposes a realtime 3D rendering architecture for view synthesis in 2D-to-3D conversion. The real-time architecture can support 60 frames per second and full HD resolution (1920×1080) on FPGA platform.
Keywords :
field programmable gate arrays; image resolution; lenses; rendering (computer graphics); video signal processing; 2D video; 2D-to-3D conversion; 3D camera; 3D display technology; 3D products; 3D projector; 3D-TV; CPU capability; FPGA platform; central processing unit; full HD resolution; hardware implementation; real-time 3D rendering; real-time architecture; realtime 3D rendering architecture; Computer architecture; Field programmable gate arrays; Glass; Hardware; Real-time systems; Rendering (computer graphics); Three-dimensional displays;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6571991