A half rate CDR with DCD cleaning up and quadrature clock calibration for 20Gbps 60GHz communication in 65nm CMOS

A half-rate clock and data recovery (CDR) circuit for 60GHz communication with 20Gbps QPSK modulation in 65nm CMOS is presented. A hybrid DC-offset cancellation loop (DCOC) is proposed to calibrate the input offset. A duty cycle distortion (DCD) cleaning up circuit is adopted to minimize the negative impact on the half rate sampling in the CML-CMOS conversion, and a quadrature clock calibration (QCC) is utilized to correct the input clock I/Q phase mismatch. The CDR is based on phase interpolator (PI) and uses the quadrature clocks from the divider of the main PLL. The whole CDR consumes less than 16mW with 1V power supply and achieves less than 1mV DC-offset, 0.2% DCD and less than 1° residual I/Q phase mismatch after calibration.