DocumentCode :
626694
Title :
A 32.8mW 60fps cortical vision processor for spatio-temporal action recognition
Author :
Seongwook Park ; Junyoung Park ; Injoon Hong ; Hoi-Jun Yoo
Author_Institution :
Dept. of Electr. Eng., KAIST, Daejeon, South Korea
fYear :
2013
fDate :
19-23 May 2013
Firstpage :
1002
Lastpage :
1005
Abstract :
In this paper, we propose a 60fps cortical vision processor modeling a hierarchical object classification model (HMAX) based on spatio-temporality in video stream. It is hard to implement a real-time hardware for HMAX operation due to its high computational cost from 2-D template matching. Three components are proposed with our improved algorithms. Class Refinement Structure (CRS) dramatically reduces a dimension of HMAX descriptors by 97.01% compared to the previous works by exploiting spatio-temporal features in video action recognition. Spatio-Temporal Memory Structure (STMS) adopts spatially adaptive window technique, and it reduces the required on-chip data bandwidth and computations per a template in S2 stage. In addition, a dual image buffer structure also reduces the required off-chip network bandwidth for processing complex hierarchical stages and numerous image spaces. As a result, the 10.8 GOPS cortical vision processor implemented in 0.13μm CMOS process achieves 60frames/sec performances for 256×256 video inputs at 200MHz operating frequency.
Keywords :
CMOS digital integrated circuits; feature extraction; image classification; image matching; image recognition; microprocessor chips; video signal processing; video streaming; 2D template matching; CMOS process; CRS; HMAX descriptor dimension; HMAX operation; STMS; class refinement structure; complex hierarchical stages; computational cost; cortical vision processor modeling; dual-image buffer structure; frequency 200 MHz; hierarchical object classification model; image spaces; off-chip network bandwidth; on-chip data bandwidth; power 32.8 mW; real-time hardware; size 0.13 mum; spatially-adaptive window technique; spatio-temporal action recognition; spatio-temporal features; spatio-temporal memory structure; video action recognition; video stream; Acceleration; Computer architecture; Correlation; Hardware; Object recognition; Real-time systems; Streaming media;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
ISSN :
0271-4302
Print_ISBN :
978-1-4673-5760-9
Type :
conf
DOI :
10.1109/ISCAS.2013.6572018
Filename :
6572018
Link To Document :
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