DocumentCode :
626697
Title :
Robust random chip ID generation with wide-aperture clocked comparators and maximum likelihood detection
Author :
Yunju Choi ; Jaeha Kim
Author_Institution :
Sch. of Electr. & Comput. Eng., Inter-Univ. Semicond. Res. Center, Seoul, South Korea
fYear :
2013
fDate :
19-23 May 2013
Firstpage :
1014
Lastpage :
1017
Abstract :
In many applications, mass-produced chips need to be tagged with individual identification numbers (i.e. chip ID). One way to do this without requiring post-fabrication programming steps is to generate the unique ID per chip exploiting random device mismatch. However, it can be prone to mis-identification due to time-varying noise that may cause a different ID to be read from the same chip each time. This paper presents a wide-aperture, low-noise clocked comparator design and a novel ID detection scheme based on maximum likelihoods (ML) that can significantly reduce the probability of mis-identification for such random chip ID generators. A prototype chip fabricated in 0.18-μm CMOS demonstrates the measured input-referred noise of the comparator as low as 265-μVrms, while preserving the wide input-referred offset distribution of 22-mVrms. As for the detection scheme, the analysis shows that when detecting 1024 unique IDs, the proposed ML detection scheme can achieve the mis-identification rate of 1.73×10-18 with 64-bits while the previous scheme based on Hamming distances (HD) would require 90-bits.
Keywords :
CMOS analogue integrated circuits; clocks; comparators (circuits); integrated circuit design; integrated circuit noise; maximum likelihood detection; probability; random processes; 1024 unique ID generation; CMOS fabrication; HD; Hamming distance; ID detection scheme; ML; input-referred noise measurement; input-referred offset distribution; maximum likelihood detection scheme; post-fabrication programming step; probability; random device mismatch; robust random chip ID generation; size 0.18 mum; time-varying noise; voltage 22 mV; wide-aperture low-noise clocked comparator design; word length 64 bit; word length 90 bit; Capacitors; Clocks; Databases; Generators; High definition video; Maximum likelihood detection; Noise;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
ISSN :
0271-4302
Print_ISBN :
978-1-4673-5760-9
Type :
conf
DOI :
10.1109/ISCAS.2013.6572021
Filename :
6572021
Link To Document :
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