Title :
A 1.7mW quadrature bandpass ΔΣ ADC with 1MHz BW and 60dB DR at 1MHz IF
Author :
Atac, Aytac ; Lei Liao ; Yifan Wang ; Schleyer, Martin ; Ye Zhang ; Wunderlich, Ralf ; Heinen, Stefan
Author_Institution :
Dept. of Integrated Analog Circuits & RF Syst., RWTH Aachen Univ., Aachen, Germany
Abstract :
This paper presents a continuous-time quadrature bandpass ΔΣ ADC that achieves 60dB DR and 67.4dB SFDR at 1MHz BW and 1MHz IF. The modulator uses capacitive feedforward architecture for the 3rd order loop filter for reduced power consumption and a local feedback loop for optimized noise shaping within the required band. The design is targeted for low power low IF receivers and it achieves a total power consumption of 1.7mW from 1.2V supply. The chip is fabricated with UMC 0.13μm technology.
Keywords :
analogue-digital conversion; circuit feedback; circuit noise; delta-sigma modulation; feedforward; filters; low-power electronics; network synthesis; 3rd order loop filter; BW; DR; IF; UMC technology; bandwidth 1 MHz; capacitive feedforward architecture; continuous-time quadrature bandpass ΔΣ ADC; frequency 1 MHz; local feedback loop; low power low IF receiver; modulator; noise figure 60 dB; noise figure 67.4 dB; noise shaping optimization; power 1.7 mW; power consumption; size 0.13 mum; voltage 1.2 V; Bluetooth; Clocks; Feedforward neural networks; Modulation; Power demand; Radio frequency; Receivers;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6572027
