Title :
Analysis of a class of decimated clock/data recovery architectures for serial links
Author :
Aziz, Pervez ; Malipatil, Amaresh
Author_Institution :
LSI Corporation, United States
Abstract :
PDF Not Yet Available In IEEE Xplore. The document that should appear here is not currently available.
Keywords :
Clocks; Computer architecture; Iterative methods; Jitter; Probability density function; Simulation; Transfer functions;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6572061
