• DocumentCode
    626736
  • Title

    Analysis of a class of decimated clock/data recovery architectures for serial links

  • Author

    Aziz, Pervez ; Malipatil, Amaresh

  • Author_Institution
    LSI Corporation, United States
  • fYear
    2013
  • fDate
    19-23 May 2013
  • Firstpage
    1175
  • Lastpage
    1178
  • Abstract
    PDF Not Yet Available In IEEE Xplore. The document that should appear here is not currently available.
  • Keywords
    Clocks; Computer architecture; Iterative methods; Jitter; Probability density function; Simulation; Transfer functions;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
  • Conference_Location
    Beijing
  • ISSN
    0271-4302
  • Print_ISBN
    978-1-4673-5760-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2013.6572061
  • Filename
    6572061
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=626736