A 0.7pJ/bit 2Gbps self-synchronous serial link receiver using gated-ring oscillator for inductive coupling communication

Author

Unsoo Ha ; Hyunwoo Cho ; Hoi-Jun Yoo

Author_Institution

Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea

fYear

2013

fDate

19-23 May 2013

Firstpage

1183

Lastpage

1186

Abstract

A low-energy self-synchronous serial link receiver for inductive coupling communication is implemented in 130nm CMOS process. The gated-ring oscillator (GRO) is proposed to combine three key building blocks (CDR, phase interpolator and PLL) used in conventional receiver resulting in energy consumption reduction. In addition, the start-up time and settling time for clock recovery can be significantly reduced due to the large loop bandwidth characteristics of the proposed GRO. As a result, the proposed serial link receiver achieves 2Gbps data rate and sub-20ns settling time while consuming 0.7pJ/bit from the 1.2V supply.

Keywords

CMOS analogue integrated circuits; clock and data recovery circuits; inductive power transmission; oscillators; phase locked loops; CMOS process; GRO; PLL; bit rate 2 Gbit/s; clock recovery; conventional receiver; energy consumption reduction; gated-ring oscillator; inductive coupling communication; large-loop bandwidth characteristics; low-energy self-synchronous serial link receiver; phase interpolator; settling time; size 130 nm; start-up time; time 20 ns; voltage 1.2 V; Clocks; Couplings; Detectors; Image edge detection; Logic gates; Receivers; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2013 IEEE International Symposium on

Conference_Location

Beijing

ISSN

0271-4302

Print_ISBN

978-1-4673-5760-9

Type

conf

DOI

10.1109/ISCAS.2013.6572063

Filename

6572063