Title :
A hardware CABAC encoder for HEVC
Author :
Bin Peng ; Dandan Ding ; Xingguo Zhu ; Lu Yu
Author_Institution :
Zhejiang Provincial Key Lab. of Inf. Network Technol., Zhejiang Univ., Hangzhou, China
Abstract :
This paper presents a hardware design of context-based adaptive binary arithmetic coding (CABAC) for the emerging High efficiency video coding (HEVC) standard. While aiming at higher compression efficiency, the CABAC in HEVC also invests a lot of effort in the pursuit of parallelism and reducing hardware cost. Simulation results show that our design processes 1.18 bins per cycle on average. It can work at 357 MHz with 48.940K gates targeting 0.13 μm CMOS process. This processing rate can support real-time encoding for all sequences under common test conditions of HEVC standard conforming to the main profile level 6.1 of main tier or main profile level 5.1 of high tier.
Keywords :
CMOS digital integrated circuits; adaptive codes; arithmetic codes; binary codes; data compression; video coding; CMOS process; HEVC standard; compression efficiency; context-based adaptive binary arithmetic coding; design process; frequency 357 MHz; hardware CABAC encoder; hardware cost reduction; hardware design; high-efficiency video coding standard; size 0.13 mum; Context; Context modeling; Encoding; Hardware; Joints; Throughput; Video coding;
Conference_Titel :
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
978-1-4673-5760-9
DOI :
10.1109/ISCAS.2013.6572110
