An FPGA co-processor for adaptive lane departure warning system

This paper presents an FPGA co-processor design for adaptive lane departure warning system, which requires intensive computation for real-time video image processing. The main functions of the co-processor include color scheme conversion, 2D filtering, transferring intensity into binary pattern using Otsu´s threshold method, and detecting lanes using Hough transform. The system design is implemented on a Xilinx Kintex FPGA with FMC DVI module connected to a camera. Our experimental tests prove the design is fully functional and the FPGA-based implementation meets the real-time requirement of reporting lane departure for practical applications.