An improved read/write scheme for anchorless NEMS-CMOS non-volatile memory

We proposed a NEMS-based anchorless memory structure with two stable mechanical states (Up and Down) for retaining data even at high operating temperate (>200^°C) [5]. Compared to the conventional anchored devices, the anchorless structure offers better scalability and can operate at lower supply voltage, which is more desirable for integration with CMOS processes. This work addresses several issues in the previous NEM memory array implementation such as shuttle oscillation due to electrostatic pendulum and non-polarity write operation. We propose a 128 × 128 NEM memory array consisting of NEM memory cells and CMOS read/write control circuits. Our proposed read/write scheme with the two-level gate control eliminates the non-polarity write issue and achieves 32% power and 14% delay improvements when compared to the previous control scheme.