DocumentCode
626816
Title
A radiation-hardened DLL with fine resolution and DCC for DDR2 memory interface in 0.13 μm CMOS
Author
Siyu Yang ; Deping Huang ; Xiaoke Wen ; Lei Chen ; Jinghong Chen
Author_Institution
Dept. of Electr. Eng., Southern Methodist Univ., Dallas, TX, USA
fYear
2013
fDate
19-23 May 2013
Firstpage
1496
Lastpage
1499
Abstract
This paper presents a radiation-hardened-by-design digital delay locked loop (DLL) for DDR2 memory interface. The DLL utilizes thermometer coding with bubble correction and phase combination to cope with single event effects (SEEs). In addition, phase interpolation and duty cycle corrector are employed to achieve both high resolution and low duty cycle distortion. The proposed DLL is designed and simulated in a 0.13 μm CMOS technology. Simulation results show that the DLL is hardened against SEEs for charge injection as large as 250 fC and can recover quickly from radiation strikes on its sensitive nodes. The DLL operates at 267 MHz with 10% input duty cycle distortion and 30 ps delay resolution. It consumes 6.3 mW of power under 1.5 V power supply.
Keywords
CMOS digital integrated circuits; charge injection; delay lock loops; CMOS technology; DCC; DDR2 memory interface; bubble correction; charge injection; duty cycle corrector; duty cycle distortion; fine resolution; frequency 267 MHz; node sensitivity; phase combination; phase interpolation; power 6.3 mW; radiation-hardened DLL; radiation-hardened-by-design digital delay locked loop; single event effects; size 0.13 mum; thermometer coding; time 30 ps; voltage 1.5 V; Clocks; Delay lines; Delays; Generators; Image edge detection; Synchronization; Tuning;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2013 IEEE International Symposium on
Conference_Location
Beijing
ISSN
0271-4302
Print_ISBN
978-1-4673-5760-9
Type
conf
DOI
10.1109/ISCAS.2013.6572141
Filename
6572141
Link To Document